Semiconductor memories include volatile memories such as DRAM, SRAM and the like, and non-volatile memories such as mask ROM, EPROM, EEPROM and the like. Of the EEPROMs, there is the so-called flash memory, which has been developed and is in use at present, which has a single transistor per memory cell.
As illustrated in FIGS. 1, 2A and 2B, this flash memory is constituted such that floating gate 14 is disposed between the channel and the gate (called control gate) of a field effect transistor (FET) which consists of source 12, drain 11 and gate 13. Programming is carried out by injecting electrons into floating gate 14 or removing electrons from floating gate 14.
FIG. 2A is a sectional view taken along line 2A--2A of FIG. 1, and FIG. 2B is a sectional view taken along line 2B--2B of FIG. 1.
Floating gate 14 indicates the shaded areas in FIG. 1, and is provided with one for each cell, while a plurality of control gates 13 are provided in a continuous form. In the drawings, reference codes 15, 16 and 17 indicate insulating layers.
When writing (programming) into the flash EEPROM, that is, when injecting charges into the floating gate, the drain and the control gate are manipulated by supplying an appropriate voltage.
When programming (writing), a voltage of 7 to 8 volts is supplied to the drain, and a voltage of 12 to 13 volts is supplied to the control gate, so that hot electrons should be produced in the channel between the source and drain. Such hot electrons are pulled by the electric field of the voltage of the control gate, and pass through the insulating layer of the gate (tunneling) and are ultimately injected into the floating gate.
Thus, the floating gate is charged with negative charge, so that the threshold voltage of the transistor is raised. Consequently, the transistor is not turned on with the normal control gate voltage, and, therefore, the transistor remains in a turned off state during normal operation.
If the cell which thus has been programmed is to be erased, the control gate and the substrate are grounded, and the drain is made to float, while a positive voltage of 13 to 15 volts is supplied to the source. Thus, electrons tunnel (Fowler Nordheim tunneling) from the floating gate to the source, so that the floating gate should lose charge. Consequently, the threshold voltage of the transistor is lowered, and the programmed contents are erased.
Such a technique for a flash memory is described in the "Solid State Circuit" Journal published by IEEE (dated October 1989, Vol. 24, No. 5, pages 1259-1263) (A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory" by V. Kynett et al.). Such a technique is further described in a speech by H. Kume, et al., in a VLSI technique conference of 1991 under the title of "A 3142 [micron square] Flash Memory Cell Technology Conformable to a Sector Erase," which was published in the Digest of Technical Papers (pages 77-78). Such a technique is further described by N. Kodama et al., under the title of "A 5 V 16 M bit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies," which was published in the same publication (pages 75-76).
In such conventional techniques, junction breakdown can occur when erasing the programmed data.
In an attempt to prevent this phenomenon, as illustrated in FIG. 2B, source 12 is made in a dual form consisting of a high concentration impurity region N+ and a low concentration impurity region N-, so that a stepped junction should be formed, thereby raising the junction breakdown voltage of the source electrode. Such a technique with a source electrode having such a junction structure is disclosed in U.S. Pat. No. 4,698,787 (dated Oct. 6, 1987). Further, in order to solve the junction problem, U.S. Pat. No. 5,077,691 (dated Dec. 31, 1991) proposes the following. A voltage of 5 volts (Vcc) is supplied to the source, and a negative voltage of -11 to -13 volts is supplied to the control gate, thereby erasing the programmed cells.
In the above described conventional techniques, when erasing the recorded data from the cell, a high voltage is supplied to the source electrode relative to the control gate. Consequently, a deep depletion region is formed in the source, and electron-hole pairs are produced. These holes receive energy from the electric field in the deep depletion region to form hot holes. These hot holes are injected into the gate insulating layer, and are caught there. Consequently, during erasing, the tunneling current is increased, and therefore over-erasing occurs. Further, due to the hot holes, there are cases in which the threshold voltage variation increases too much. Such problems are described by S. Haddad et al., in "Degradation Due to Hole Trapping in Flash Memory Cells," published in IEEE Electron Device Letters (Volume 10, No. 3, pages 117-119, March 1989).
Further, in the conventional techniques, during programming or erasing, the gate oxide (indicated by reference code 20 in FIG. 2B) has to be maintained about 100 Angstroms in order for electrons to be tunneled. Consequently, the manufacturing process is fastidious, and the yield is low. Efforts are being made to increase the yield of flash memory devices by improving the quality of the tunneling oxide. For example, such efforts include reducing the level of capture of electrons and electron holes in the tunneling oxide, lowering the heavy metal contamination of the channel of the tunneling oxide and the source-drain region, inhibiting charging of the gate by the etching plasma, and the like. The yield with such techniques, however, still is low compared with DRAM and SRAM devices, and, the thinner the gate oxide, the more serious is the problem of gate disturbance, which increases the threshold voltage.